1. Field of the Invention
The present invention relates to an electronic control apparatus incorporating therein a microprocessor used for controlling an internal combustion engine for vehicle and, more particularly, to a vehicle-mounted electronic control apparatus that includes a serial communication function to mutually communicate an input/output signal or the like.
2. Background Arts
Hitherto, several vehicle-mounted electronic control systems that carries out an information exchange by serial communication between a pair of microprocessors sharing functions have been disclosed in, for example, the Japanese Patent Publication (unexamined) No. 269409/1995, the Japanese Patent Publication (unexamined) No. 128065/1993, the Japanese Patent Publication (unexamined) No. 13912/1995, etc. Among those known control systems, the Japanese Patent Publication (unexamined) No. 269409/1995 disclosed a technique arranged as follows. That is, in the case of transmitting data from a main CPU for controlling a fuel to a sub CPU for controlling a transmission, a SUM value of whole data of a CPU on the transmitting side is calculated, an equivalent value to this SUM value is added to a rearmost part of a data stream (data message) and the resultant data stream is transmitted. Then a CPU on the receiving side calculates a SUM value of the whole data resulted from removing the rearmost data and compares the SUM value with the rearmost data thereby checking whether or not abnormality is present in the received data.
Further, the Japanese Patent Publication (unexamined) No. 128065/1993 disclosed a technique arranged for controlling an internal combustion engine using two CPUs in the following manner. In this known technique, a hand-shaking line is provided between a master CPU and a slave CPU, and after completing a receiving process of the data transmitted from the master CPU, the slave CPU transmits a signal indicating completion of the receiving process via the hand-shaking line. The master CPU receives the signal indicating completion of the receiving process and then starts transmitting the next data thereby making it possible to transmit data at a high speed without fail.
Furthermore, the technique disclosed in the Japanese Patent Publication (unexamined) No. 13912/1995 relates to communication between a CPU and a serial communication block not having any CPU. This communication technique is arranged in such a manner as to provide shift registers on both CPU and serial communication sides respectively, and a shift destination of high-order-bit from one of the shift registers is established to be low-order-bit of the other shift register. Accordingly the CPU simultaneously executes transmitting instruction data and receiving reply data to shorten a processing time.
It is a recent trend that the vehicle-mounted electronic control system has to control varieties of contents, and contents to be processed in the microprocessor and information exchange between the microprocessors have been complicated. For example, in a control system including a master station and substations, it has becomes a problem to be solved how to transmit and receive efficiently a large amount of information communication mutually between the master station and the substations are selected.
In view of overcoming such a problem, when studying the mentioned technique disclosed in the Japanese Patent Publication (unexamined) No. 269409/1995, for example, it is certain that reliability in data communication can be achieved, but the technique is not always arranged so as to select a large amount of communication information and efficiently transmit and receive them.
When studying the technique disclosed in the Japanese Patent Publication (unexamined) No. 128065/1993, it is found that this technique intends to carry out a high-speed communication continuously without duplication. For that purpose, a signal indicating completion of receiving is transmitted via the hand-shaking line, and the master CPU executes the next transmission after receiving the signal indicating the completion of receiving. Further a data list representing type, sequence or amount of data to be data-exchanged is stored in a program memory of each microprocessor, and a data list conforming to various communication periods is to be selected. However, a problem exits in that this known communication technique is deficient in freedom of carrying out a variety of communication.
Furthermore, when studying the technique disclosed in the Japanese Patent Publication (unexamined) No. 13912/1995, a shift register is provided on each of transmitting and receiving sides, and serial-parallel conversion is conducted, thereby transmitting instruction data and receiving input data are done at the same time to shorten a processing time. However, a problem exists in that the technique is not always arranged so as to be capable of selecting a large amount of communication information, and efficiently transmitting and receiving them.
The present invention has been made to solve the above-discussed problems, and has an object of providing communication control means having a high degree of freedom in which, even if a data amount of down-communication from a master station to a substation is not balanced with that of up-communication from the substation to the master station and such an unbalance fluctuates depending on operating conditions of a microprocessor thereby occurring any jam or delay in communication to or from one station, such delay does not affect communication to and from the other station, and the latest information can be added to the jammed and delayed communication data.
Another object of the invention is to provide a vehicle-mounted electronic control apparatus capable of putting together and cutting down a large amount of irregular up-communication data, and suppressing the delay in up-communication from the substation to the master station which delay is liable to occur in communication operation state.
A vehicle-mounted electronic control apparatus according to the invention includes: a microprocessor in which a program memory, an operational RAM, an interface circuit providing a connection to a first vehicle-mounted sensor group, an interface circuit providing a connection to a first electrical load group, and a serial-parallel converter for master station are bus-connected; and a common control circuit in which a serial-parallel converter for substation that is serial-connected to the serial-parallel converter for master station, an interface circuit providing a connection to a second vehicle-mounted sensor group, and an interface circuit providing a connection to a second electrical load group are bus-connected, the common control circuit being provided with first storage means, second storage means, abnormality determination means, distribution storage means, reply packet generation means, and reply packet composing means. In this vehicle-mounted electronic control apparatus, the first storage means stores in sequential order command data, address data, write data, sum check collation data received by the serial-parallel converter for substation via the serial-parallel converter for master station. The abnormality determination means monitors lack or mixing of any bit information in the data stored in the first storage means. The distribution storage means transfers the write data to a device memory of a specified address based on the stored address data and write data when the command data stored in the first storage means is a write/setting command accompanied by the write data. The reply packet generation means selects reply data based on the result determined by the abnormality determination means and the command data, combines the foregoing reply data with the address data to synthesize reply information. The reply information generated by the reply packet generation means is stored in sequential order into the second storage means, and read out on the basis of a preceding input/preceding output while evacuating a delay in replying. The reply packet composing means composes in a predetermined order plural reply information to be supplied to the serial-parallel converter for substation based on the reply information read out from the second storage means. Then the reply packet composing means generates additional data based on the latest information and adds those data to the delayed and held reply information to send back resultant reply information.
In the vehicle-mounted electronic control apparatus of above arrangement, down-communication can be continued without delay by the second storage means that conducts a preceding input/preceding output operation even if any delay occurs temporarily in up-communication. Further the latest readout information can be added to the delayed reply data, and the resultant reply information can be sent back. As a result, freedom in transmit/receiving timing is improved thus making it possible to carry out an efficient serial communication.
Another vehicle-mounted electronic control apparatus according to the invention includes: a microprocessor in which a program memory, an operational RAM, an interface circuit providing a connection to a first vehicle-mounted sensor group, an interface circuit providing a connection to a first electrical load group, and a serial-parallel converter for master station are bus-connected; and a common control circuit in which a serial-parallel converter for substation that is serial-connected to the serial-parallel converter for master station, an interface circuit providing a connection to a second vehicle-mounted sensor group, and an interface circuit providing a connection to a second electrical load group are bus-connected, the common control circuit being provided with a selection data memory.
In this vehicle-mounted electronic control apparatus, down-serial data transmitted from the serial-parallel converter for master station to the serial-parallel converter for substation include an output/setting packet and a readout request packet. Up-serial data sent back from the serial-parallel converter for substation to the serial-parallel converter for master station include a readout reply packet and a regular reply packet. The output/setting packet includes at least a drive output to the second electrical load group, or write destination address data and write data for transmitting constant setting data to a setting device bus-connected to the serial-parallel converter for substation. The readout request packet includes at least readout destination address data for requesting a transmission of ON/OFF information provided by the second vehicle-mounted sensor group. The readout reply packet includes at least readout data having a preliminarily specified address as reply data to the readout request packet. The regular reply packet includes at least reply data for sending back an input signal from the second vehicle-mounted sensor group in sequential order or in a lump. The selection data memory is a memory containing information of irregular data that are stored in a memory having one or plural specified addresses by the common control circuit, and are sent back from the serial-parallel converter for substation to the serial-parallel converter for master station. The information is sent back to the mastery station serial-parallel converter by the readout reply packet or the regular reply packet.
In the vehicle-mounted electronic control apparatus of above arrangement, the microprocessor can perform mutual exchange of information between the regular down-communication provided by the output/setting packet and the irregular communication provided by the readout request packet. Further the common control circuit can regularly reply information using the regular reply packet, and can store irregular data in the selection data memory based on the determination of the common control circuit to be capable of sending back the irregular data while updating them in sequential order. As a result, an efficient communication can be achieved without normally replying useless information.